1. Field of the Invention
Generally, the subject matter disclosed herein relates to the field of integrated circuits, and, more particularly, to a method of manufacturing P-channel transistor devices. More particularly, the subject matter disclosed herein relates to improved methods of forming P-channel transistor devices with channels comprising silicon-germanium materials.
2. Description of the Related Art
Integrated circuits formed on semiconductor wafers typically include a large number of circuit elements, which form an electric circuit. In addition to active devices such as, for example, field effect transistors and/or bipolar transistors, integrated circuits can include passive devices such as resistors, inductors and/or capacitors. In particular, during the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer.
A MOS transistor, for example, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer.
The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. Moreover, the gate dielectric material may be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for obtaining a high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques and may also contribute to less pronounced performance gain due to mobility degradation, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the process adaptations associated with device scaling.
Moreover, current technologies providing more compact and functional electronic devices require semiconductor devices with exactly adjusted threshold voltages at differ threshold voltage levels. Conventionally, some measures for tuning the threshold voltage involve performing implantation processes which are adapted for each semiconductor device type individually for appropriately setting the required threshold voltage to a desired value. For example, halo implantation processes are conventionally performed for adjusting the threshold voltage when fabricating modern semiconductor devices, such as MOS transistors, with short channels, e.g., less than 50 nm channel length. Herein, the accordingly formed halo regions encompass source and drain extension regions of each transistor towards the channel. Basically, halo regions are regions doped with dopants of similar conductivity type as those that are present in the surrounding active region, therefore representing counter-doped regions with regard to the source and drain doping. However, the dopant concentration in halo regions is higher as compared to the surrounding active regions. At present, halo regions represent conventional measures employed for reducing so-called short channel effects which appear at small gate lengths scales and short channel lengths scales, respectively. It is apparent that, with devices of various device types or flavors possibly being formed in different regions across a single semiconductor wafer, individual tuning in each region becomes necessary in order to minimize unwanted variations. The result is a complex process flow, even posing the risk of introducing unacceptably high variations of the threshold voltage across the wafer due to the inclusion of new processes.
With respect to improved control of the threshold voltages and enhanced channel conductivities, i.e., carrier mobility, PMOS SOI devices have been introduced that comprise strained silicon germanium channels (cSiGe).
FIGS. 1a and 1b show an example of the conventional CMOS FDSOI manufacturing of a semiconductor device by integrating strained SiGe channel PFET and silicon channel NFET devices. As shown in FIG. 1a, on an SOT wafer comprising a substrate 1, a thin buried oxide layer 2 and a silicon layer 3, an NFU area and a PFET area are defined. An SiGe layer 4 is epitaxially formed on a portion of the silicon layer 3 of the PFET region. After thermal oxidation enhanced condensation, the SiGe/silicon bi-layer is converted into a single SiGe layer 4′ as shown in FIG. 1b. Typically, the single SiGe layer 4′ has a thickness in a range from about 8-12 nm. The thin buried oxide layer 2 of the SOI wafer may have a comparable thickness of about 10-25 nm. After completion of the condensation process performed to obtain the single SiGe layer 4′, an isolation structure 5, for example, a shallow trench isolation (STI), is formed in order to electrically isolate the NFET area from the PFET area.
However, in the art, the problem arises that, during the condensation process, the thin SiGe layer 4′ that is not sufficiently stabilized by the thin buried oxide layer 2 starts warping. The resulting deformation of the SiGe layer 4′ negatively affects the reliability and performance of the resulting PFETs.
Therefore, the present invention provides techniques for manufacturing PFET devices comprising SiGe channels wherein the above-described problems are efficiently mitigated.